Device processing

Complete processing lines are available for the production of III-V based optoelectronic and microelectronic devices and circuits, located in the 800 m² and 400 m² of processing clean rooms (class 10000 or better) in Marcoussis and Palaiseau respectively. Processing building blocks have been developed, qualified and tuned to cover the many requirements of the variety of devices and III-V material systems :

  • Optical and electron beam lithography
  • Wet and high resolution dry-etching (IBE, RIE, ICP …)
  • Dielectric and metal deposition and annealing, Zn diffusion on 3” wafers
  • Anti-reflection coating with in situ ellipsometry
  • Wafer thinning and dicing
Quantum Well Infra-red Photodetector (QWIP) arrays for dual wavelength detection, with a pitch of 25 µm. Each GaAs-based array (visible on the left photograph) is made of 384 x 388 pixels (one pixel is visible on the right photograph); arrays exhibit a pixel operability larger than 99.5 % without any cluster larger than 5 pixels.
Transition between a 1.5 µm wide ridge waveguide and a tapered W1 (only one missing row of holes) photonic crystal waveguide, patterned in an InP-based multi-layer structure. This patterning is achieved using e-beam lithography and ICP etching. Reflection coefficient of the transition with a W3 (three missing rows) can be as low as -35 dB, illustrative of the excellent etching characteristics.
40 Gbit/s InP-based Heterojunction Bipolar Transistor (HBT) IC. This circuit is fabricated on 3” wafers with an epitaxial structure grown by Gas Source MBE (GS-MBE). 3-layer metal interconnects are used in such mixed-signal ICs, with a transistor count typically between 30 and 100 and a functional yield between 50 and 70%.